CRC Computation

1. Append 4 zeros to the message at the right.
2. Perform division by generator polynomial on message polynomial.
3. Replace the zeros at the end of message with the remainder obtained.

MTCMOS

1. In MTCMOS technique the sleep transistors are given high threshold to control sub threshold leakage current.
2. In normal CMOS transistor there is some leakage current is flowing even when the transistors are off or on.
3. The high threshold transistors are kept in between the power supply rails.
4. Low threshold is chosen for the transistors used to implement functional blocks to have high performance.

Disadvantages Of Existing Solution.

1. The leakage power in MOS transistors reduces the life time of battery.
2. The leakage power in the CDFF still not avoidable because no gating is employed to switch off the circuit    when not in use.
3. Use of MTCMOS technique the standby power is saved.

Problem Statement

Pulse triggered flip flops are of two types implicit and explicit pulse triggered but explicit pulse triggered is advantageous in high performance and low power consumption.One of the fastest pulse triggered flipflop is Explicit pulsed data close to output flipflop. As there are unnecessary consumption of power due to switching activities in the internal nodes of (Ep-DCO) flipflop.These switching activities can be reduced by using the conditional discharge technique.

Introduction

In high performance microprocessor circuits, registers are the main parts for processing information.
MTCMOS (multi threshold CMOS) technique saves the leakage power during standby mode operations and hence, enhances the circuit performance for long battery life applications.We find that, using both MTCMOS and CDFF, improve the performance and also consume low power where we can employ power gating more effectively. First we simulate CDFF using with and without MTCMOS to prove that proposed MTCMOS CDFF is the best of fast pulse triggered flipflops which achieves low power and high performance. We go for applications of 4 bit shift register, pseudo random bits generation, serial and parallel CRC using this MTCMOS CDFF which saves 20% of power as that using CDFF and Ep-DCO in these applications.